1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a high voltage generating circuit preserving charge pumping efficiency.
A claim of priority is made to Korean Patent Applications No. 10-2004-0024893 and No. 10-2004-0037688, filed respectively on Apr. 12, 2004 and May 27, 2004. The disclosures of these Korean Applications are incorporated herein by reference in their entirety.
2. Description of the Related Art
A high-density Dynamic Random Access Memory (DRAM) typically operates at a low power supply voltage of 1.5 V or 1.8 V. Unfortunately, the low power supply voltage tends to cause sluggishness in the performance of the DRAM circuit. For example, the low power supply voltage generally causes sense amplifiers to operate slowly and bit lines to precharge slowly. In order to address these and other issues, a DRAM typically provides a boosted voltage of 3.0 V or more to a word line, a bit line, or a sense amplifier. The boosted voltage is typically provided by boosting the low power supply voltage of the DRAM using a high voltage generating circuit.
A high voltage generating circuit providing a boosted voltage is disclosed, for example, in U.S. Pat. No. 6,414,882.
FIG. 1 illustrates a conventional high voltage generating circuit.
Referring to FIG. 1, a high voltage generating circuit 500 comprises pump circuits 504a and 504b. Pump circuits 504a and 504b operate in a cooperative manner such that an output node VCCP of charge pump circuit 500 is driven by only one of pump circuits 504a or 504b at any given time.
Pump circuits 504a and 504b are coupled so that whenever output node VCCP is driven by pump circuit 504b, excess charge apparent at a boost node 522b in pump circuit 504b is discharged into a boost node 522a in pump circuit 504a. As a consequence, charge in high voltage generating circuit 500 is conserved, and therefore, an output current of high voltage generating circuit 500 is maintained, thus reducing power consumption. Boost nodes 522a and 522b are precharged by a power supply having a power supply voltage VCC.
FIG. 2 is a waveform timing diagram illustrating the operation of the high voltage generating circuit shown in FIG. 1.
Referring to FIG. 2, a precharge transistor 524a is turned on by a signal P2B2 between times t2 and t3, thus precharging boost node 522a to power supply voltage VCC. Between times t2 and t3, a current path is formed between boost node 522a and the power supply via precharge transistor 524a. Where a voltage apparent at boost node 522a is larger than power supply voltage VCC, the voltage apparent at boost node 522a is reduced to power supply voltage VCC, as illustrated by a solid line PIA in FIG. 2. Reducing the voltage apparent at boost node 522a reduces charge pumping efficiency in high voltage generating circuit 500. Accordingly, there is a need to develop a high voltage generating circuit preserving charge pumping efficiency.